Analog IP Filter Cores With Embedded Test For Design Reuse

Current technology allows for the integration of complete systems onto a single chip. These systems on chip (SoC) are increasingly designed by connecting together large pre-designed and verified modules, called cores, with the advantage being a faster design cycle. The development of third party Intellectual Property (IP) cores is a rapidly expanding industry, and whereas initially these were nearly all digital, analog IP cores are now representing a greater proportion of this market. The testing of corebased SoCs is clearly essential but very complex with the test of analog cores being particularly challenging. Embedded test techniques move some of the test hardware onchip and are the most efficient way to overcome existing problems. The main objective for analog IP core development is to design a core with given specifications as quickly as possible. The main objective for embedded analog IP core test is to derive a test solution with best fault coverage considering all design tradeoffs. The project will eventually address both of these objectives in terms of analog filters. Switched Current (SI) techniques, can implement analog functions on the most basic of digital processes and from the detailed review of SI in Chapter 2, we conclude that SI may be particularly suitable for implementing analog IP cores. Considering different filter design techniques has also lead us to the conclusion that wave filter design, detailed in Chapter 3, may also be suitable as it is ideal for implementation in SI with the resulting regular architecture lending itself to automated generation. A library of hierarchical cells for filter design has been created allowing rapid prototyping, to simulation level, of wave filter cores. Up to this point, the most significant shortcoming is poor performance of the filters created. Future work will therefore involve improving the overall performance and finding the best design compromise in terms of given factors. Work also need to be undertaken to derive lowlevel device dimensions from higher level specifications and constraints. Following this, an embedded test solution can be developed, fulfilling the second objective. The outcome of this research will be a CAD tool capable of generating complete filter IP cores with embedded test. Analog IP Filter Cores With Embedded Test For Design Reuse 2